Useful VLSI Links

Here are some useful links on VLSI design and verification:

Tips:

http://www.sutherland-hdl.com/quiz-and-tips.php

Setup and hold times:

http://nigamanth.net/vlsi/2007/09/13/setup-and-hold-times/

One-hot encoding:

http://only-vlsi.blogspot.com/2008/06/one-hot-encoding.html
http://asics.chuckbenz.com/detailed_one_hot.htm

Synchronizers:

http://www.edn.com/article/490034-Practical_design_for_transferring_signals_between_clock_domains.php
http://www.edn.com/index.asp?layout=article&articleid=CA276202
http://www.edn.com/contents/images/276202.pdf
http://www.velocityreviews.com/forums/t376740-synchronizer-theory-and-question.html
http://www.mofeel.net/210-comp-arch-fpga/1589.aspx

FIFO:

http://www.asic-world.com/tidbits/fifo_depth.html

Binary systems:

http://www2.cs.uh.edu/~jhuang/JCH/LD/chap01.html
http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/1008f68f858d40/c7dbd404b882df4d?lnk=st&q=#c7dbd404b882df4d
http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/b28d399ab79c6812/469beb60578f0200?lnk=st&q=#469beb60578f0200

DSP:

http://www.geoffknagge.com/fyp/

Counters:

http://www.play-hookey.com/digital/synchronous_counter.html
http://www.wisc-online.com/objects/index_tj.asp?objID=DIG4203

State Machines:

http://www.vlsi-world.com/content/view/42/34/

VLSI books:

http://www.allaboutcircuits.com/vol_4/chpt_11/3.html
http://books.google.com/books?id=Oygh3IDUTgsC&pg=PA608&lpg=PA608&dq=flow+table+merger+diagram&source=web&ots=N7lNi3-X8s&sig=O5olPsmZlQU2ank52wUEw-0-RAc&hl=en&sa=X&oi=book_result&resnum=5&ct=result#PPA607,M1
http://books.google.com/books?id=tIp7FK81-wMC&pg=PA739&lpg=PA739&dq=flow+table+merger+diagram&source=web&ots=afaRCt8qdO&sig=G-h0fODzrtAl9TV1D_Z4uHFy-xc&hl=en&sa=X&oi=book_result&resnum=2&ct=result

Testbenches:

http://www.testbench.in/

SystemVerilog:

http://www.systemverilog.in/
http://www.eda.org/sv/SystemVerilog_3.1a.pdf
http://www.doulos.com/knowhow/sysverilog/tutorial/clocking/
http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=1728
http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=2120
http://verificationguild.com/modules.php?name=Forums&file=viewtopic&p=12470
http://verificationguild.com/modules.php?name=Forums&file=viewtopic&p=10923
http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=3095
http://www.reference.com/search?q=SystemVerilog
http://electrosofts.com/systemverilog/
http://jwebb-design.com/ee/howto/using_perl_with_sv.shtml
http://www.project-veripage.com/sva_7.php
http://www.project-veripage.com/dpi_tutorial_1.php
http://www.cdnusers.org/Forums/tabid/52/forumid/66/postid/3218/view/topic/Default.aspx http://groups.google.com/group/comp.lang.verilog/browse_thread/thread/531f08a9574862fc# http://www.findthecat.com/vera2sv/
http://www.soccentral.com/results.asp?CatID=488&EntryID=25580
http://vlsihomepage.com/2007/10/20/procedural-statements-and-operators-in-systemverilog/
http://vlsihomepage.com/2007/10/19/procedural-blocks-in-systemverilog/
http://asic-tutor.com/Verilog/Examples.html
http://sv-verif.blogspot.com/2009/11/systemverilog-tip-watch-out-enum-and.html

Verification:

http://www.intelligentdv.com/blog/223/systemverilog-reset-transaction-transactor-library-released/

Perl:

http://www.doulos.com/knowhow/perl/
http://blog.vinceliu.com/2008/02/non-greedy-regular-expression-matching.html
http://t16web.lanl.gov/Kawano/gnuplot/webplot/index-e.html

Tools:

http://www.kwcpa.com/tools/

Standards:

http://www.ieee802.org/1/
http://www.scte.org/standards/index.cfm?pID=59
http://www.eda-stds.org/sdf/sdf_3.0.pdf
http://www.freemodelfoundry.com/sdfbnf.html

Interview questions:

http://vlsifaq.blogspot.com/2007/10/digital-design-interview-questions.html
http://www.edaboard.com/ftopic293902.html